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www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
FEATURES:
- - - - - - - - - Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4 W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion
IDT74LVC16540A
DESCRIPTION:
This 16-bit buffer driver is built using advanced dual metal CMOS technology. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. To ensure the highimpedance state during power up or power down, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capabiltiy of the driver. All pins of this 16-bit buffer/line driver can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16540A has been designed with a 24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance.
Drive Features for LVC16540A: - High Output Drivers: 24mA - Reduced system switching noise
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1O E1 1O E2
1 48
2O E1 2O E2
24 25
47 1A 1
2
1Y1
36 2A 1
13
2Y 1
TO SEVEN O TH ER CH ANN ELS
TO SEVEN OTHER CH ANN ELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4700/-
www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1O E1 1Y 1 1Y 2
ABSOLUTE MAXIMUM RATINGS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1O E2 1A 1 1A 2
(1)
Unit V C mA mA mA
LVC Link
1 2 3 4 5 6 7 8 9 10 11 SO48-1 12 SO48-2 SO48-3 13 14 15 16 17 18 19 20 21 22 23 24
Symbol VTERM TSTG IOUT IIK IOK ICC ISS
Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
Max. - 0.5 to +6.5 - 65 to +150 - 50 to +50 - 50 100
GND
1Y 3 1Y 4
GND
1A 3 1A 4
VCC
1Y 5 1Y 6
VCC
1A 5 1A 6
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
1Y 7 1Y 8 2Y 1 2Y 2
GND
1A 7 1A 8 2A 1 2A 2
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC Link
GND
2Y 3 2Y 4
GND
2A 3 2A 4
NOTE: 1. As applicable to the device type.
VCC
2Y 5 2Y 6
VCC
2A 5 2A 6
PIN DESCRIPTION
Pin Names xOEx xAx xYx Description 3-State Output Enable Inputs (Active LOW) Data Inputs 3-State Outputs
GND
2Y 7 2Y 8 2O E1
GND
2A 7 2A 8 2O E2
FUNCTION TABLE (each 8-bit buffer) (1)
xOE1 Inputs xOE2 L L X H xAx L H X X Outputs xYx
H
SSOP/ TSSOP/ TVSOP TOP VIEW
L L H X
L Z Z
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
c 1998 Integrated Device Technology, Inc.
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DSC-123456
www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40OC to +85OC
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC 3.6 VIN 5.5V(2) Quiescent Power Supply Current Variation One input at VCC - 0.6V other inputs at VCC or GND -- -- -- -- -- -- -- - 0.7 100 -- -- -- 50 - 1.2 -- 10 10 500 A
LVC Link
Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VI = 0 to 5.5V VO = 0 to 5.5V
Min. 1.7 2 -- -- -- --
Typ.(1) -- -- -- -- -- --
Max. -- -- 0.7 0.8 5 10
Unit V V A A A V mV A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
LVC Link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C.
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www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per buffer/driver Outputs enabled Power Dissipation Capacitance per buffer/driver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 34 2 Unit pF pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xYx Output Enable Time xOEx to xYx Output Disable Time xOEx to xYx Output Skew(2) Min. VCC = 3.3V0.3V Max. 4.5 5.9 6.3 Min. 1 1.5 1.6 Max. 3.7 4.8 5.9 500 Unit ns ns ns ps

NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc VCC / 2 150 150 30 V V mV mV pF
LVC Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse (1, 2) Generator VIN D.U.T. 500 CL VOUT VLOAD Open GND
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
RT
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
LVC Link
NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL
LVC Link
tSU
tH
GND Open
tREM
OUTPUT SKEW - tsk (x)
VIH INPUT VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2 VT VOL
SYNCHRONOUS CONTROL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
tPLH1
tPHL1
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
LVC Link
VT
tSK (x)
tSK (x)
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link
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www..com IDT74LVC16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX LVC X Bus-Hold XX Family XXXX Device Type XX Package Temp. R ange
PV PA PF 540A 16
Shrink Small Outline P ackage Thin Shrink Small Outline Package Thin Very Small Outline Package 16-Bit Buffer/Driver with 3-State Outputs Double-Density, 24mA
Blank 74
No Bus-hold -40C to +85C
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